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17.9 A 62µA Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer

By Matti Paavola, Mika Kämäräinen, Jere Järvinen, Mikko Saukoski, Mika Laiho and Kari Halonen

Abstract

Capacitive accelerometers [1] have advantages such as zero static bias current, the capability of high sensitivity, and excellent thermal stability, making their use in low-power applications attractive. In this paper, an interface ASIC designed for a capacitive 3-axis micro-accelerometer [2] is presented. The die area and power dissipation are reduced by using time-multiplexed sampling and duty cycles down to 0.3%. The block diagram of the interface with the sensor element [2] is shown in Fig. 17.9.1. The element is composed of four proof masses. The front-end converts the capacitive acceleration information to a voltage. Two algorithmic ADCs convert the acceleration and temperature information into the digital domain. These ADCs are powered down between their conversion cycles. The clock generator provides a 2MHz system clock (SYSCLK), and a 1 to 50MHz microcontroller unit clock (MCUCLK). The latter makes possibl

Year: 2014
OAI identifier: oai:CiteSeerX.psu:10.1.1.413.940
Provided by: CiteSeerX
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