Skip to main content
Article thumbnail
Location of Repository

Performance Evaluation and Optimization of Dual-Port SDRAM Architecture for Mobile Embedded Systems

By Hoeseok Yang, Sungchan Kim, Hae-woo Park, Jinwoo Kim and Soonhoi Ha

Abstract

Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local memories and the shared memory for both processors. In order to keep memory consistency from simultaneous accesses of both ports, every access to the shared memory should be protected by a synchronization mechanism, which can result in substantial access latency. We propose two optimization techniques by exploiting the communication patterns of target application: lock-priority scheme and static-copy scheme. Further, by dividing the shared bank into multiple blocks, we enable simultaneous accesses to different blocks and achieve considerable performance gain. Experiments on a virtual prototyping system show a promising result that we achieve about 20-50 % performance gain compared to the base DPSDRAM architecture

Topics: dual-port SDRAM, mobile embedded system
Year: 2014
OAI identifier: oai:CiteSeerX.psu:10.1.1.413.5426
Provided by: CiteSeerX
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • http://citeseerx.ist.psu.edu/v... (external link)
  • http://www.cecs.uci.edu/~paper... (external link)
  • Suggested articles


    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.