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Thesis Proposal: Out-Of-Core Parallel Discrete-Event Simulation

By Anna L. Poplawski


With today's processor speeds and the current state of parallel discrete-event simulation, the amount of available physical memory is now the limiting factor in determining the size of some simulations. This does not need to be true. We believe it is possible to run many simulations in an out-of-core setting. Out-of-core techniques have been applied to other areas in order to e#ciently use disk storage as part of the memory hierarchy; however, parallel simulation has little in common with most of these other applications. Therefore, there are many problems to examine before an e#cient out-of-core parallel simulator can be built. This proposal describes these problems and some possible solutions. It also presents one potential design for an outof -core simulator. Results obtained from a model of this design demonstrate that out-of-core simulation is a reasonable option. Contents 1 Introduction 1 1.1 Out-of-core Applications . . . . . . . . . . . . . . . . . . . . . . . . . . ..

Year: 2000
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