Multi-gate architectures such as gate-all-around (GAA) Si nanowires are the promising candidates for aggressive CMOS downscaling due to the immunity to the issues regarding short channel effect, improved subthreshold slope and optimized power consumption. On the other hand, Si nanowires represent excellent mechanical properties e.g. yield strength of 10±2 %  in comparison to 3.7 % for bulk Si , a strong motivation to be used as interesting exclusive platforms for innovative nanoelectronic applications e.g. novel strain engineering techniques for carrier transport enhancement in multi-gate 3D suspended channels - or local band-gap modulation using>4 GPa uniaxial tensile stress in suspended Si channels to enhance band-to-band tunneling current in multi-gate Tunnel-FETs , all without plastic deformation and therefore, no carrier mobility degradation in deeply scaled channels. In this paper, we demonstrate the integration of local oxidation  and metal-gate strain  technologies to induce 3.3%/5.6 GPa uniaxial tensile strain/stress in 2 µm long suspended Si nanowire MOSFETs, the highest process-based stress record in MOSFETs until now, by elastic local buckling. Fig. 1 represents the fabrication process to make GAA uniaxially tensile strained Si nanowire MOSFETs from a 100 mm (100) Unibond SOI substrate with 1×10 18 cm-3 phosphorous channel doping. Highly doped accumulation-mode was chosen as the operation regime to mainly simplify the process in nanoscale 
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