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Techniques for Yield Enhancement of VLSI Adders 1

By Zhan Chen and Israel Koren


For VLSI application-specific amys and other regular VLSI circuits, two techniques are available for yield enhancement, namely defect-tolerance and layout modifications. In this paper, we compare these two yield enhancement appruaches by using adders as an ezample. Our yield projections indicate that the layout modification technique is more eficient when the defect density is low, while reconjiguration is more eficient for a high defect density. However, f ” the point of the view of effective yield, the layout modification is superior to defect tolerance in the practical range of defect density.

Year: 2013
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