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Clocked FSM Synthesis considering Real Time Constraints

By Wolf-Dieter Tiedemann and Universitt Passau

Abstract

. This paper presents a synthesis technique for synchronous controllers that satisfy real time constraints when realized as a clocked finite state machine that is supplied with a prespecified clock rate. The controller needs to be specified as a Timed Automaton, a representation that could for instance be derived from a timing diagram translation. Result is a Mealy machine graph that generally contains purely time-consuming states. 1 Introduction As microprocessor technology takes entry to more and more ranges of application, the specific requirements there lead to the identification of always new classes of systems. Accordingly, each class calls for specific design techniques that focus on the particular points of emphasis. Such classes, which came up just recently, are for instance open, distributed, embedded, or reactive systems. These systems are mostly control-oriented, ie. their crucial particularities affect the control path, not the data path, and concentrate on communication ..

Year: 2007
OAI identifier: oai:CiteSeerX.psu:10.1.1.36.9754
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