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High-reliability Fault Tolerant Digital Systems in Nanometric Technologies: Characterization and Design Methodologies

By C. Bolchini, A. Miele, Politecnico Di Milano, M. Ottavi, S. Pontarelli, A. Salsano, C. Metra, M. Omaña, D. Rossi, M. Sonza Reorda, L. Sterpone, M. Violante, S. Gerardin, M. Bagatin and A. Paccagnella

Abstract

While the shrinking of minimum dimensions of integrated circuits till tenths of nanometers allows the integration of millions of gates on the single chip, it also implies the growth of the importance of effects that could reduce the reliability of circuits. In particular, the reduced integration step, the reduced supply voltage that lowers the noise immunity, the growing power needs, the eventual integration of both digital and analog circuits on the same chip and the highly growing of radiation sensitivity [1], [2], [3] require an accurate evaluation of possible reliability reduction for the occurrence of: • permanent faults due to the aging of device materials [4], the interruptions of metal interconnections due to electromigration [5] or the crack of the insulation oxide of transistor [6]; • transient faults, known as Single Event Effects (SEE)

Year: 2013
OAI identifier: oai:CiteSeerX.psu:10.1.1.353.582
Provided by: CiteSeerX
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