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By Salvatore Pontarelli, Pedro Reviriego, Chris J. Bleakley and Juan Antonio Maestro

Abstract

Abstract — This paper studies the problem of designing a low complexity Concurrent Error Detection (CED) circuit for the complex multiplication function commonly used in Digital Signal Processing circuits. Five novel CED architectures are proposed and their computational complexity, area and delay evaluated in several circuit implementations. The most efficient architecture proposed reduces the number of gates required by up to 30% when compared with a conventional CED architecture based on Dual Modular Redundancy. Compared to a Residue Code CED scheme, the area of the proposed architectures is larger. However, for some of the proposed CEDs delay is significantly lower with reductions exceeding 30 % in some configurations

Topics: Index Terms — Complex multiplication, Concurrent Error Detection, Fault Tolerance
Year: 2013
OAI identifier: oai:CiteSeerX.psu:10.1.1.353.554
Provided by: CiteSeerX
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