Skip to main content
Article thumbnail
Location of Repository

FUNCTIONAL BLOCK DIAGRAM

By 

Abstract

Dual 16-bit ADC in enhanced package for extended temperature range of −55°C to +85°C 1.8 V analog supply operation LVDS output SNR: 80.5 dBFS at 30 MHz input and 105 MSPS data rate SFDR: 93 dBc at 30 MHz input and 105 MSPS data rate Low power: 328 mW per channel at 105 MSPS Integer 1-to-8 input clock divider IF sampling frequencies up to 300 MHz Analog input range of 2.7 V p-p Optional on-chip dither Integrated ADC sample-and-hold inputs Differential analog inputs with 500 MHz bandwidth ADC clock duty cycle stabilizer (DCS

Year: 2013
OAI identifier: oai:CiteSeerX.psu:10.1.1.353.4046
Provided by: CiteSeerX
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • http://citeseerx.ist.psu.edu/v... (external link)
  • http://www.analog.com/static/i... (external link)
  • Suggested articles


    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.