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Dual 16-bit ADC in enhanced package for extended temperature range of −55°C to +85°C 1.8 V analog supply operation LVDS output SNR: 80.5 dBFS at 30 MHz input and 105 MSPS data rate SFDR: 93 dBc at 30 MHz input and 105 MSPS data rate Low power: 328 mW per channel at 105 MSPS Integer 1-to-8 input clock divider IF sampling frequencies up to 300 MHz Analog input range of 2.7 V p-p Optional on-chip dither Integrated ADC sample-and-hold inputs Differential analog inputs with 500 MHz bandwidth ADC clock duty cycle stabilizer (DCS

Year: 2013
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