Skip to main content
Article thumbnail
Location of Repository

System level modeling of Networks-on-Chip for power estimation and design space exploration

By Martin Gag, Tim Wegner, Andreas Tockhorn and Dirk Timmermann


With a fast rising productivity and even faster rising integration densities, i.e., designproductivity-gap, energy and power dissipation are critical topics in high level system design more than ever. Thermal aware system design, reliable power delivery, and the overall energy dissipation are only few crucial design properties. In this work we present a framework based on SystemC, enabling the modeling and simulation of many-core systems reverting to Networks-on-Chip as their communicational infrastructure. The transaction level communication model is clock cycle accurate, yielding a fast yet concise functional simulation. The framework is enriched by parameters concerning technology node and floorplanning and by a thermal model of the eventual chip. Thereby, power estimation and on-chip temperature distribution can be evaluated in an early design phase. Furthermore, the framework is supplemented by extensions enabling an extensive and detailed design space exploration, namely proactive thermal management and thermal aware task mapping. 1

Year: 2013
OAI identifier: oai:CiteSeerX.psu:
Provided by: CiteSeerX
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • (external link)
  • (external link)
  • Suggested articles

    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.