The yield of a VLSI chip depends, among other factors, on the sensitivity of the chip to defects occurring during the fabrication process. To predict this sensitivity, one usually needs to compute the so-called critical area (Ac) which re ects how many and how large the defects must be in order to result in a circuit failure. The main computational problem in yield estimation is to calculate Ac e ciently for complicated, irregular layouts. A novel approach is suggested for this problem that results in an algorithm that will solve it e ciently. This paper provides an interactive accurate and fast method for the rapid evaluation of critical area as a design tool with good visual feedback to allow layout improvement for higher yield. The algorithm is compared to other yield-prediction methods, which use either the Monte-Carlo approach (VLASIC) or a deterministic approach (SCA), and is shown to be faster. It also has the advantage that it can graphically show a detailed `defect sensitivity map ' that can assist a chip designer in improving the yield of his/her layout
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