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Wire Length and Via Reduction for Yield Enhancement

By Venkat K. R. Chiluvuri and Israel Korent

Abstract

Wire length reduction along with via minimization results in better performance and higher yield for VLSI circuits. In this paper we present a wire length reduction algorithm for channel routing. The results of our algorithm for a set of benchmark examples are presented. The algorithm produces near optimal results for most of the examples. Surprisingly, our algorithm outperforms most of the previously proposed via minimization algorithms as well. Our results show that both wire length and via minimization problems are closely related to each other but their optimal solutions don't necessarily coincide

Topics: design for yield, layout synthesis, yield enhancement, channel routing, via reduction, wire length minimization, defect tolerance
Year: 1996
OAI identifier: oai:CiteSeerX.psu:10.1.1.352.6976
Provided by: CiteSeerX
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