Abstract – Microelectronics packaging and testing are increasingly being conducted on devices in strip form. Once charged, strips may discharge through a pin on one IC. The resulting damage is simulated by a new ESD test method: the Charged Strip Model (CSM). CSM withstand voltages are inversely proportional to strip capacitances. Thus, IC’s that are immune to Charged Device Model (CDM) damage may be susceptible to CSM damage. Since CSM discharge events may have far more energy than other real-world ESD events, CSM damage can be easily mistaken for EOS damage. CSM damage can be minimized via appropriate strip designs and actions to minimize strip charging during manufacturing. I
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