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On area and yield considerations for fault-tolerant VLSl processor arrays

By Israel Koren, Melvin, A. Breuer and Senior Member

Abstract

Abstract-Fault-tolerance is undoubtedly a desirable property of In Section 11 of this work we investigate the cost in chip area any processor array. However, increased design and implementation of including fault-tolerance in the architecture of a processor costs should be expected when fault-tolerance is being introduced into array. Since various fault-tolerant techniques are possible, we the architecture of a processor array. When the processor array is implemented within a single VLSI chip, need means to evaluate these techniques and choose the one these cost increases are directly related to the chip silicon area. Thus, for which the chip area iS best utilized. the increase in area should be weighed against the improved perfor- Another consequence of an increase in the chip area might mance of the gracefully degrading fault-tolerant processor array. In be a reduction in the wafer yield. At present, the yield of some addition, a larger chip area might reduce the wafer yield to an unac- large area chips is 15 percent and lower, and a further reducceptable level making the use of fault-tolerant VLSI processor arrays tion in the wafer yield might lower It to levels which are unimpractical. acceptable The objective of this paper is to devise wafe performance measures for acceptable to the semductor semiconductor industry. Itrye the evaluation of the effectiveness and area utilization of various In Section Jll we analyze the reduction in yield due to the fault-tolerant techniques. Another goal is to analyze the reduction in inclusion of fault-tolerance and we investigate the possibility wafer yield and investigate the possibility of yield enhancement through of yield enhancement through added redundancy. redundancy. Index Terms-Area utilization, computational availability, fault- II. AREA CONSIDERATIONS tolerance, processor array, reconfiguration strategies, redundancy, Fault-tolerance strategies which do not mask the effect of VLSI, wafer yield. faults by massive redundancy employ two steps. The first on

Year: 1984
OAI identifier: oai:CiteSeerX.psu:10.1.1.352.6568
Provided by: CiteSeerX
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