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Hardware mechanisms for memory authentication

By Edward Suh, Dwaine Clarke, Blaise Gassend, Marten Van Dijk, Srini Devadas, G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten Van Dijk and Srinivas Devadas

Abstract

Memory integrity verification is a useful primitive when implementing secure processors that are resistant to attacks on hardware components. This paper proposes new hardware schemes to verify the integrity of untrusted external memory using a very small amount of trusted on-chip storage. Our schemes maintain incremental multiset hashes of all memory reads and writes at run-time, and can verify a sequence of memory operations at a later time. We study the advantages and disadvantages of the two new schemes and two existing integrity checking schemes, MACs and hash trees, when implemented in hardware in a microprocessor. Simulations show that the new schemes outperform existing schemes of equivalent functionality when integrity verification is infrequent.

Year: 2003
OAI identifier: oai:CiteSeerX.psu:10.1.1.322.4219
Provided by: CiteSeerX
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