. Dynamic voltage and frequency scaling has been identified as one of the most e#ective ways to reduce power dissipation. This paper discusses a compilation strategy that identifies opportunities for dynamic voltage and frequency scaling of the CPU without significant increase in overall program execution time. The paper introduces a simple, yet e#ective performance model to determine an e#cient CPU slow-down factor for memory bound loop computations. Simulation results of a superscalar target architecture and a program kernel compiled at di#erent optimizations levels show the potential benefit of the proposed compiler optimization. The energy savings are reported for a hypothetical target machine with power dissipation characteristics similar to Transmeta's Crusoe TM5400 processor. 1 Introduction Modern architectures have a large gap between the speeds of the memory and the processor. Several techniques exist to bridge this gap, including memory pipelines (outstanding rea..