Increasingly demanding computation requirements and tighter energy constraints have motivated distributed and/or hierarchical register file (dhrf) organizations as a mean to efficiently sustain a sufficient alu utilization in processors targeting embedded applications with many alus. Compared to conventional centralized register file organizations, dhrfs lead to tighter coupling between register allocation and instruction scheduling: since latencies to register files are non-uniform, register allocation affects access latencies, thus in turn affects instruction scheduling. To avoid this phase order-1 ing problem, researchers have proposed performing instruction scheduling and register allocation simultaneously. While these unified register allocation and instruction scheduling algorithms address the phase ordering problem, they can be susceptible to scheduling deadlocks: the scheduling algorithm cannot make any forward progress due to its previous decisions. Previous unified algorithms either ignore the scheduling deadlock issue or rely on architectural assumptions with respect to connectivity between register files and functiona
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