Skip to main content
Article thumbnail
Location of Repository

Hierarchical Instruction Register Organization

By David Black-schaffer, James Balfour, William J. Dally, Vishal Parikh and Jongsoo Park

Abstract

Abstract — This paper analyzes a range of architectures for efficient delivery of VLIW instructions for embedded media kernels. The analysis takes an efficient Filter Cache as a baseline and examines the benefits from 1) removing the tag overhead, 2) distributing the storage, 3) adding indirection, 4) adding efficient NOP generation, and 5) sharing instruction memory. The result is a hierarchical instruction register organization that provides a 56 % energy and 40 % area savings over an already efficient Filter Cache. Index Terms — energy-efficient embedded processor architecture, hierarchical and distributed instruction register organization, VLIW instruction delivery I

Year: 2013
OAI identifier: oai:CiteSeerX.psu:10.1.1.309.4202
Provided by: CiteSeerX
Download PDF:
Sorry, we are unable to provide the full text but you may find it at the following location(s):
  • http://citeseerx.ist.psu.edu/v... (external link)
  • http://cva.stanford.edu/projec... (external link)
  • Suggested articles


    To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.