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Algorithm Design and Performance Evaluation of Equivalent CMOS Model

By Parvinder S. S, Iqbaldeep Kaur, Amit Verma, Inderpreet Kaur and Birinderjit S. Kalyan

Abstract

Abstract—This work is a proposed model of CMOS for which the algorithm has been created and then the performance evaluation of this proposition has been done. In this context, another commonly used model called ZSTT (Zero Switching Time Transient) model is chosen to compare all the vital features and the results for the Proposed Equivalent CMOS are promising. In the end, the excerpts of the created algorithm are also included and V2 charges the capacitor at two different values. Let the V1 voltage is 5 volts, then the charged stored in the capacitor is Q = C

Topics: T
Year: 2013
OAI identifier: oai:CiteSeerX.psu:10.1.1.308.905
Provided by: CiteSeerX
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