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Megabit-Class Size-Configurable 250-MHz SRAM Macrocells with a Squashed-Memory-Cell Architecture

By Nobutaro Shibata Hiroshi, Hiroshi Inokawa and Keiichiro Tokunaga


this paper, a 1-Mb SRAM test chip was fabricated with an advanced 0.35-m CMOS/bulk process. The SRAM has demonstrated 250-MHz operation with a 2.5-V typical power supply. Also, 100-mW power dissipation was obtained at a practical operating frequency of 150-MHz

Topics: per-bitline architecture, current-sense amplier, squashed memory cell, trench isolation
Year: 1999
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