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Performance Analysis of Hardware Barrier Synchronization

By M. O\u27Keefe and H. Dietz

Abstract

Synchronization among cooperating processors is a critical issue in the performance of high speed multiprocessors. For current Multiple Instruction stream Multiple Data stream (MIMD) computers synchronization cost is high. Hence, these architectures can execute only large granularity parallelism efficiently. In this report we study a new hardware synchronization technique, known as a hardware barrier. Machines using this technique are known as barrier MIMDs. Analytic and simulation studies are employed to show that hardware barrier synchronization can outperform the more common directed synchronization techniques. Barrier synchronization can be viewed as a static synchronization mechanism similar to the implicit synchronization of Very Long Instruction Word architectures (VLIWs). We study two variations of hardware barrier synchronization previously developed, static and dynamic, and suggest a new hybrid approach

Publisher: 'Purdue University (bepress)'
Year: 1989
OAI identifier: oai:docs.lib.purdue.edu:ecetr-1680
Provided by: Purdue E-Pubs
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