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A Study of Memory Access Patterns in Irregular Parallel Codes Using Hardware Counter-Based Tools

By Oscar G. Lorenzo, Juan A. Lorenzo, J. C. Cabaleiro, Dora B. Heras Marcos Suárez and Juan C. Pichel

Abstract

Abstract — This work presents the development of a series of tools to simplify both EARs (Event Address Registers) counters reading and programming in parallel codes. These tools allow EAR counters access in a user friendly workspace. The next tools have been developed: A tool for inserting, in a simple and intuitive manner, the code needed to monitor and program hardware counters in a parallel program. Another tool takes as input the data obtained by the monitored parallel code and shows them in a comprehensive and detailed way. These tools were used to carry out a study of parallel irregular codes and to validate a data reordering technique used to optimize locality of memory accesses in the SpMxV (sparse matrix vector product) problem. Access characterization is one of the main issues dealing with the problem of improving performance of irregular accesses. This is specially true in parallel shared memory platforms

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Year: 2012
OAI identifier: oai:CiteSeerX.psu:10.1.1.218.1545
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