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Schedulability Analysis of Preemptive and Non-preemptive EDF on Partial Runtime-reconfigurable Fpgas

By Nan Guan, Qingxu Deng, Zonghua Gu, Wenyao Xu and Ge Yu

Abstract

Field Programmable Gate Arrays (FPGAs) are very popular in today’s embedded systems design, and Partial Runtime-Reconfigurable (PRTR) FPGAs allow HW tasks to be placed and removed dynamically at runtime. Hardware task scheduling on PRTR FPGAs brings many challenging issues to traditional real-time scheduling theory, which have not been adequately addressed by the research community compared to software task scheduling on CPUs. In this paper, we consider the schedulability analysis problem of HW task scheduling on PRPR FPGAs. We derive utilization bounds for several variants of global preemptive/non-preemptive EDF scheduling, and compare the performance of different utilization bound tests

Topics: General Terms, Algorithms, Design, Performance Additional Key Words and Phrases, Real-Time Scheduling, Reconfigurable Devices, FPGA
Year: 2000
OAI identifier: oai:CiteSeerX.psu:10.1.1.216.7763
Provided by: CiteSeerX
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