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System-on-Chip and ASIC Design High-Performance System Design Co-Simulation Between SystemC and a New Generation Emulator

By Cedric Alquier, Stephane Guerinneau, Lauro Rizzatti and Luc Burgun

Abstract

In this paper, we examine a co-simulation solution between SystemC and a new generation emulator called ZeBu. SystemC is a C++ hardware description library that supports design modeling from the RT level to the system level. SystemC is part icularly effective for IP and embedded systems verification. ZeBu is a hardware verification product built on a PCI card with the latest Xilinx Virtex-II FPGA devices. First, we discuss a verification scenario based on a SystemC test bench stimulating the design mapped in the emulation board via bit-signals/vectors, and propose an implementation solution. This method offers the simplicity of use but limits its performance to few hundred KHz. To push the performance into the MHz, we then propose to raise the level of abstraction using the SystemC channels in a transactional mode. This approach allows a transaction level systemC test bench to be easily connected to the emulator for high-speed performance

Year: 2003
OAI identifier: oai:CiteSeerX.psu:10.1.1.194.4456
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