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A Fast Algorithm to Instantly Predict FPGA SSN for Various I/O Pin Assignments

By Geping Liu, Altera Corporation, Zhuyuan Liu, Altera Corporation, Kundan Ch, Altera Corporation, Kaiyu Ren, Altera Corporation, Nafira Daud and Altera Corporation Abstract

Abstract

This paper proposes a fast algorithm to instantly predict simultaneous switching noise (SSN) for FPGA I/O pin assignments. In this algorithm, SSN has two distinct components: the mutual inductive coupling and the power distribution network (PDN) noise. Each component can be individually quantified through matrix manipulations and measurement results. This algorithm is independent of any simulator engines, thereby avoiding time-consuming system-level SPICE-like simulations. The predictions from this algorithm are correlated well with direct bench measurements. This paper also describes how to build an SSN measurement automation system to efficiently implement this algorithm, and presents a measurement data interpretation methodology. Author(s) Biography Dr. Geping Liu is a supervisory member of technical staff in the characterization group at Altera Corporation. His work and interests include signal integrity, power integrity, and electromagnetic compatibility (EMC) designs in high-speed digital systems, and development and application of numerical and experimental methods in resolving signal integrity and EMC problems. He received his BSEE and MSEE from Tsinghu

Year: 2008
OAI identifier: oai:CiteSeerX.psu:10.1.1.192.2615
Provided by: CiteSeerX
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