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This section provides information on the different types of phase-locked loops (PLLs). The feature-rich enhanced PLLs assist designers in managing clocks internally and also have the ability to drive off chip to control system-level clock networks. The fast PLLs offer general-purpose clock management with multiplication and phase shifting as well as highspeed outputs to manage the high-speed differential I/O interfaces. This section contains detailed information on the features, the interconnections to the logic array and off chip, and the specifications for both types of PLLs. This section contains the following chapter: Chapter 1, PLLs in Stratix II and Stratix II GX Device

Year: 2011
OAI identifier: oai:CiteSeerX.psu:10.1.1.192.2223
Provided by: CiteSeerX
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