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Practical chip-centric electro-thermal simulations

By Renaud Gillon, Patricia Joris, Herman Oprins, Bart Vandevelde, Adi Srinivasan and Rajit Chandra

Abstract

Full-chip dynamic electro-thermal simulation is achieved by coupling a circuit simulator and a thermal solver. By letting both simulations run with their specific time-step, a higher computational efficiency is achieved. A scheduler synchronizes temperatures in the circuit simulator and dissipation patterns in the thermal solver on an 'as-necessary ' basis. The 3D geometry for the thermal solver is generated automatically from the layout data-base and cross-referenced to the netlist to allow automatic extraction of power-dissipation from circuit simulations. In order to obtain realistic thermal responses for smart-power chips containing large driver transistors, it is essential to define the boundary conditions appropriately and account for package and PCB transients. To do so, the simulation domain is extended to cover the full package body, and uniform boundary conditions are defined to account for the thermal impedance of the PCB and for convection and radiation. Validation results are shown for the case of an SOIC package. Work is on-going on QFN and other power-packages

Year: 2008
OAI identifier: oai:CiteSeerX.psu:10.1.1.192.1588
Provided by: CiteSeerX
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