A computer system is useless unless it can interact with the outside world through input/output (I/O) devices. II0 systems are complex, including aspects such as memory-mapped operations, interrupts, and bus bridges. Often, IJO behavior is described for isolated devices without a formal description of how the complete II0 sys-~ tern behaves. The lack of an end-to-end Jrstem description makes the tasks of system programmers and hardware implementors more dificult to do correctly. This paper proposes a framework for formally describing I/O architectures called Wisconsin II0 (WIO). WI0 extends work on memory consistency models (that formally specify the behavior of normal memory) to handle considerations such as memorymapped operations, device operations, interrupts, and operations with side effects. Specifically, WI0 asks each processor or device that can issue k operation types to speci ’ ordering requirements in a k X k table. A system obeys WI0 if there always exists a total order of all operations that respects processor and device ordering requirements and has the value of each “read ” equal to the value of the most recent “write ” to that address. This paper then presents examples of WI0 specifications for systems with various memory consistency models including sequential consistency (SC), SPARC TSO, an approximation of Intel LA-32, and Compaq Alpha. Final & we present a directory-based implementation of an SC system, and we sketch a proof which shows that the implementation conforms to its WI0 specijcation.
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