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An FPGA-Based Video Compressor for H.263 Compatible Bit Streams

By G. Lienhart, R. Männer and G. Lienhart R. Männer

Abstract

This paper presents an FPGA architecture for video encoding according to the H.263 standard for video teleconferencing systems. The implementation is based on an off-the-shelf FPGA and is embedded in a PCI plug-in card with on-board SRAM plus external SRAM. The most complex part of the H.263 protocol, a base-line encoder, was implemented. The strategies, which have been applied to build the complex encoding operations, are treated in this paper. The complete application is able to operate at 30 MHz. This leads to a maximum compression speed of 120 Mbit/s allowing simultaneous real-time operation of several video streams in a single reconfigurable chip. Enhanced coding options can also become implemented with present-day FPGAs. The use of FPGA technology enables the adaptation of hardware to various protocols and environments by software and therefore saves development time and hardware costs

Topics: B.6.1 [Hardware- Logic-Design- Design Styles] General Terms Performance, Design. Keywords Video Compressor, FPGA, H.263, Distributed Arithmetic
Year: 2001
OAI identifier: oai:CiteSeerX.psu:10.1.1.19.9782
Provided by: CiteSeerX
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