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A Technology-Scalable Architecture for Fast Clocks and High ILP

By Karthikeyan Sankaralingam, Ramadass Nagarajan, Doug Burger and Stephen W. Keckler

Abstract

CMOS technology scaling poses challenges in designing dynamically scheduled cores that can sustain both high instruction-level parallelism and aggressive clock frequencies. In this paper, we present a new architecture that maps compiler-scheduled blocks onto a two-dimensional grid of ALUs. For the mapped window of execution, instructions execute in a dataflow-like manner, with each ALU forwarding its result along short wires to the consumers of the result. We describe our studies of program behavior and a preliminary evaluation that show that this architecture has the potential for both high clock speeds and high ILP, and may offer the best of both the VLIW and dynamic superscalar architectures.

Year: 2001
OAI identifier: oai:CiteSeerX.psu:10.1.1.19.9524
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