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Parallelizing Circuit Simulation - A Combined Algorithmic And Specialized Hardware Approach

By Jacob White and Nicholas Weiner

Abstract

Accurate performance estimation of high-density integrated circuits requires the kind of detailed numerical simulation performed in programs like ASTAP[1] and SPICE[2]. Because of the large computation time required for such prograins when applied to large circuits, accelerating numerical simulation is an important problem. Parallel processing promises to be a viable approach to accclerating the simulation of large circuits. This paper presents an approach which exploits the parallelism in the simulation problem at two levels. A relaxation algorithm is used to break the circuit into loosely coupled blocks which can be computed in parallel, and spe- cial purpose hardware is used to exploit parallelism inside the block computation

Year: 2007
OAI identifier: oai:CiteSeerX.psu:10.1.1.19.8999
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