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Exploiting Schedule Slacks for Rate-Optimal Power-Minimum Software Pipelining

By Hongbo Yang, R. Govindarajan, Guang R. Gao, George Cai and Ziang Hu


Increasing power consumption in high performance processors and the proliferation of embedded systems demand new compiler techniques geared toward both high performance and low power. Software pipelining, an effective compiler optimization to exploit instruction level parallelism across loop iterations, has been studied extensively. However, previous software pipelining methods focus on performance only. This paper presents a software pipelining method that reduces power consumption while keeping performance optimality. This is accomplished as schedule slacks exist for non-critical instructions even in performance optimal schedules, and by exploiting the slack appropriately, it may be possible to reduce the number of functional units used in the schedule

Year: 2002
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