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Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers

By Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro and Behnaam Aazhang

Abstract

A real-time VLSI architecture is designed for Multiuser Channel Estimation, one of the core baseband processing operations in wireless base-station receivers. Future wireless base-station receivers will need to use sophisticated algorithms to support extremely high data rates and multimedia. Several features in these algorithms that can help meet real-time requirements are not utilized effectively in DSPs. These features, such as bit level arithmetic and parallel structure, can be revealed and well exploited by task partitioning the algorithms. We modify the channel estimation algorithm for a reduced complexity fixed-point hardware implementation. We show the complexity and hardware required for three different area-time tradeoffs': an area-constrained, a timeconstrained and an area-time efficient architecture. The area-constrained architecture achieves low data rates with minimum hardware, which may be used in 'picocell' base-stations. The timeconstrained solution exploits the entire available parallelism and determines the maximum theoretical data rates. The area-time efficient architecture meets real-time requirements with minimum area overhead. The orders-of-magnitude difference between area and time constrained solutions reveals significant inherent parallelism in the algorithm. All VLSI solutions exhibit better time performance than a previous DSP implementation

Topics: sridhar, skrishna, cavallar, aaz} @ rice. edu
Year: 2000
OAI identifier: oai:CiteSeerX.psu:10.1.1.19.3828
Provided by: CiteSeerX
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