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FUNCTIONAL BLOCK DIAGRAM

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Abstract

Start-up frequency accuracy: <±100 ppm (determined by VCXO reference accuracy) Zero delay operation Input-to-output edge timing: <150 ps Dual VCO dividers 14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS 14 dedicated output dividers with jitter-free adjustable delay Adjustable delay: 63 resolution steps of period of VCO output divider Output-to-output skew: <50 ps Duty cycle correction for odd divider settings Automatic synchronization of all outputs on power-up Absolute output jitter: <150 fs at 122.88 MHz Integration range: 12 kHz to 20 MHz Broadband timing jitter: 124 fs Digital lock detect Nonvolatile EEPROM stores configuration settings SPI- and IC-compatible serial control port Dual PLL architecture PLL1 Low bandwidth for reference input clock cleanup with external VCXO Phase detector rate of 300 kHz to 75 MHz Redundant reference inputs Auto and manual reference switchover modes Revertive and nonrevertive switching Loss of reference detection with holdover mode Low noise LVCMOS output from VCXO used for RF/IF synthesizers PLL2 Phase detector rate of up to 250 MHz Integrated low noise VCO APPLICATIONS LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentatio

Topics: OSC_IN, OSC_IN
Year: 2011
OAI identifier: oai:CiteSeerX.psu:10.1.1.188.5488
Provided by: CiteSeerX
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