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TO 2GHZ LOCKING RANGE AND ±35PS JITTER

By Chao Xu, Winslow Sargeant, Kenneth R. Laker and Jan Van Der Spiegel

Abstract

[Abstract] A fully integrated phase-locked loop (PLL) fabricated in a 0.24μm, 2.5v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-persecond clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30MHz up to 2GHz in 0.24μm CMOS technologies. Also it has very low peak-to-peak jitter less than ±35ps at 1.25GHz output frequency. 1

Year: 2011
OAI identifier: oai:CiteSeerX.psu:10.1.1.187.1554
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