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By Prof Preeti and Ranjan Panda


With the widening performance gap between processor and memory, the performance issues of data caches are becoming more relevant. This has led to the importance of compiler optimization techniques which exhibit high data locality in the memory accesses of the programs. These techniques require a detailed and accurate information about the amount of reuse between the memory accesses. Hence a method for evaluating data cache performance statically is essentially required. The existing analytical models target mainly isolated loop nests either by using a probablistic approach which leads to loss of accuracy or by using an exact model of data cache behavior which compromises with the performance of the approach. We present an analytical model that is capable of analysing not only isolated loop nest fragments, but also complete programs modeled as flat loop nests with if statements and statically predictable memory accesses. Central to the whole approach are the computation of minimum and maximum memory access vectors corresponding to each cache line and each memory reference which coupled with an algorithmic reuse analysis for intra and inter loop reuse provides an elegant method for determining statically the performance of a data cache. The algorithmic reuse analysis allows the user to compute the amount of reuse in a program at a desired level of accuracy, thus giving a tool in the hands of the user to choose between accuracy and performance tradeoffs. Implemented within the SUIF compiler framework, the experimental results indicate more accurate cache miss estimates in a substantially shorter amount of time than currently existing analytical or simulation techniques to model data cache behavior

Year: 2011
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