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The AES Encryption Circuit on a Reconfigurable Hardware

By J. Sripornprasert and P. Chongstitvatana

Abstract

Abstract-This work presents an AES encryption circuit implemented by a special type of machine called “Hardware Multiplexing ” (HWMX). Hardware Multiplexing is a kind of reconfigurable embedded processor. By using dynamic reconfiguration concept, HWMX operates AES Algorithm correctly with efficient resources. HWMX consists of two cores 1) Register Bank and 2) Reconfigurable Core. The first part stores temporal results for next round computation. The second part, an important core of HWMX, processes as a reconfigurable system. This approach allows HWMX to pursue AES encryption application by splitting AES circuit into four segments and execute one segment per round, putting the temporal result of each segment into Register Bank. By using time-multiplexing hardware the resource consumed is less than a conventional circuit. I

Year: 2011
OAI identifier: oai:CiteSeerX.psu:10.1.1.184.2467
Provided by: CiteSeerX
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