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A Tightly-Coupled Processor-Network Interface

By Christopher F. Joerg and Dana S Henry

Abstract

Careful design of the processor-network interface can dramatically reduce the software overhead of interprocessor communication. Our interface architecture reduces communication overhead five fold in our benchmarks. Most of our performance gain comes from simple, low cost hardware mechanisms for fast dispatching on, forwarding of, and replying to messages. The remaining improvement can be gained by implementing the network interface as part of the processor's register file. For example, using our hardware mechanisms a register-mapped interface can receive, process, and reply to a remote read request in a total of two RISC instructions. We have implemented an RTL model of an off-chip memory-mapped interface which provides our hardware mechanisms. Our industrial partner, Motorola, is implementing a similar network interface on-chip in an experimental version of the 88110 processor

Year: 1992
DOI identifier: 10.1145/143371.143497
OAI identifier: oai:CiteSeerX.psu:10.1.1.18.3383
Provided by: CiteSeerX
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