In the area of switching architecture, we propose a new point of view in order to obtain a simple architecture ensuring high performance and good growth capability. This paper presents the BSS based on a bus structure conforming with Asynchronous Transfer Mode (ATM) requirements. A two-stage structure has been adopted to facilitate modular expansion which allows the construction of a large-scale ATM switching system (10000x10000). This study deals with the BSS basic performance parameters : cell delay and cell loss probability, under a uniform traffic pattern, to dimension the output buffer size. It has been shown that when the input traffic is Bernoulli, the internal traffic streams are bursty. The interstage traffic is consequently modelled by an "ON/OFF" process which parameters are derived from the analysis of the output process of a first stage switching element. Discrete event simulations are used to validate the model. Keywords ATM, Switching Architecture, performance evaluation..