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SOC Test-Architecture Optimization for the Testing of Embedded Cores and Signal-Integrity Faults on Core-External Interconnects

By Qiang Xu and Yubin Zhang

Abstract

The test time for core-external interconnect shorts and opens is typically much less than that for core-internal logic. Therefore, prior work on test-infrastructure design for core-based system-ona-chip (SOC) has mainly focused on minimizing the test time for core-internal logic. However, as feature sizes shrink for newer process technologies, the test time for signal integrity (SI) faults on interconnects cannot be neglected. The test time for SI faults can be comparable to, or even larger than, the test time for the embedded cores. We investigate the impact of interconnect SI tests on SOC test-architecture design and optimization. A compaction method for SI faults and algorithms for test-architecture optimization are also presented. Experimental results for the ITC’02 benchmarks show that the proposed approach can significantly reduce the overall testing time for core-internal logic and core-external interconnects

Topics: Categories and Subject Descriptors, B.7.3 [Integrated Circuits, Reliability and Testing— Testability General Terms, Reliability, Design, Algorithms Additional Key Words and Phrases, Core-based system-on-chip, interconnect testing, test-access mechanism (TAM, test scheduling
Year: 2010
OAI identifier: oai:CiteSeerX.psu:10.1.1.160.9961
Provided by: CiteSeerX
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