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Low cost instruction cache designs for tag comparison elimination

By Youtao Zhang and Jun Yang

Abstract

Tag comparison elimination (TCE) is an effective approach to reduce I-cache energy. Current research focuses on finding good tradeoffs between hardware cost and percentage of comparisons that can be removed. For this purpose, two low cost innovations are proposed in this paper. We design a small dedicated TCE table whose size is flexible both horizontally (entry size) and vertically (number of entries). The design also minimizes interactions with the I-cache. For a 64-way 16K cache, the new design reduces the tag comparisons to 4.0 % with a fraction only 20 % of the hardware cost of the way memoization technique [5]. The result is 40 % better compared to a recent proposed low cost design [2] of comparable hardware cost

Topics: Low-Power Instruction Cache
Publisher: ACM Press
Year: 2003
OAI identifier: oai:CiteSeerX.psu:10.1.1.160.7555
Provided by: CiteSeerX
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