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A Reconfigurable Hardware Based Embedded Scheduler for Buffered Crossbar Switches

By Lotfi Mhamdi, Christopher Kachris and Stamatis Vassiliadis


In this paper, we propose a new internally buffered crossbar (IBC) switching architecture where the input and output distributed schedulers are embedded inside the crossbar fabric chip. As opposed to previous designs, where these schedulers are spread across input and output line cards, our design allows the schedulers to have cheap and fast access to the internal buffers, optimizes the flow control mechanism and makes the IBC more scalable. We employed the Xilinx Virtex-4FX platform to show the feasibility of our proposal and implemented a reconfigurable hardware based IBC switch with the maximum port count that we could fit on a single chip. The experiments suggest that a 24 × 24 IBC switch running a 10 Gbps port speed and a clock cycle time of 6.4 ns can be implemented

Topics: Architecture and Design General Terms Algorithms, Design, Performance Keywords Scheduling, Buffered Crossbar Fabric, Reconfigurable Hardware
Year: 2006
DOI identifier: 10.1145/1117201.1117223
OAI identifier: oai:CiteSeerX.psu:
Provided by: CiteSeerX
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