“Systems on Silicon ” has been an oft-repeated phrase of the last couple years. The ability to pack more and more gates onto a single IC has made this buzz phrase a reality and brought many issues to the forefront: Intellectual Property concerns, sub-micron design & verification methodologies, speed & size hurdles, entirely new or rejuvenated strategies such as cycle-based simulation and formal methods. This is all fine, but somewhere away from the sexy, leading-edge design arenas tackling million-gate designs, there are still boards being made to put all these Systems-On-Silicon; no one has yet proposed free-floating ASICs holographically connected to the rest of the universe. These boards with their attendant glue logic and other off-the-shelf logical components may still need to be simulated either alone or with their valuable ASIC cargo. The Free Model Foundation, a not-for-profit corporation, was formed by myself and 3 other engineers, who were working at TRW Inc. at the time. Our motivation was brought about by the lack of easily available board-level VHDL simulation models. Our goals were and are to encourage the use of standards-based board-level simulation by posting our findings, utilities, and simulation models to the public domain. “We ” in this paper refers to the FMF, either working on our own, or previously working for TRW Inc
To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.