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High-Level Modeling of Network-on-Chip

By Supervisor Prof, Jens Sparsø, Co-supervisor Ph. D, Mikkel Bystrup Stensgaard, Matthias Bo Stuart (s, Matthias Bo Stuart and Kgs Lyngby

Abstract

This report describes the design, implementation and testing of a high-level model of an asynchronous network-on-chip called MANGO that has been developed at IMM, DTU. The requirements to the model are twofold: It should be timing accurate, which allows it to be used in place of MANGO, and it should have a high simulation speed. For these purposes, different approaches to modeling network-on-chip and asynchronous circuits have been investigated. Simulation results indicate a simulation speedup on a magnitude of a factor 1000 over the current implementation of MANGO, which is implemented as netlists of standard cells. Acknowledgements This Master of Science project has been carried out at Informatics and Mathematical Modelling at the Technical University of Denmark in the spring and summer of 2006. I would like to thank my fellow students Morten Sleth Rasmussen and Christian Place Pedersen for thorough discussion of different issues that popped up along the way. I would also like to thank Tobias Bjerregaard, who created the current implementation of MANGO, for invaluable discussions on the inner workings of MANGO. I am grateful to Shankar Mahadevan for a kick-start discussion on how to model MANGO. I would especially like to thank my supervisor Jens Sparsø and my co-supervisor Mikkel Bystrup Stensgaard for invaluable guidance and discussions. ii

Topics: Contents iv
Year: 2006
OAI identifier: oai:CiteSeerX.psu:10.1.1.135.8196
Provided by: CiteSeerX
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