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A New low Power CMOS Full Adder

By Damu Radhakrishnan

Abstract

Low power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronics products. In this regard many innovative designs for basic logic functions using pass transistors and transmission gates appeared in the literature recently. But they were all designed mostly by intuition and cleverness of the designer. Hence in this paper a formal design procedure for the design of a minimal transistor CMOS XOR-XNOR cell is presented, that is fully compensated for threshold voltage drop in MOS transistors. This new cell can reliably operate when the power supply voltage is scaled down, as long as due consideration is given to the sizing of the MOS transistors during the initial design step. A formal design approach for a full adder cell using the new XOR-XNOR cell is also presented. 1

Year: 1999
OAI identifier: oai:CiteSeerX.psu:10.1.1.135.7356
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