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Logic Design for On-Chip Test Clock Generation -- Implementation details AND IMPACT ON DELAY TEST QUALITY

By Matthias Beck, Olivier Barondeau, Martin Kaibel and et al. Frank Poehl

Abstract

This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for onchip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation, meant to reduce test vector count and to increase test quality, are discussed. ATPG results for the proposed techniques are given

Year: 2005
OAI identifier: oai:CiteSeerX.psu:10.1.1.135.6790
Provided by: CiteSeerX
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