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Efficient Synchronization Primitives for large-scale cache-coherent multiprocessors

By James R. Goodman, Mary K. Vernon and Philip J. Wwst

Abstract

AbstreetThis paper proposes a set of efficient primitives for process synchronization in muitiprocessors. The only assumptions made in developing the set of primitives are that hardware combining is not implemented in the hter-connect, and (in one case) that the interconnect supports broadcast. The primitives make use of synchronization bits (syncbits) to provide a simple mechanism for mutual exclu-sion. The proposed implementation of the primitives includes efEcient (Le. kxal) busy-waiting for syncbit & In addition, a hardware-supported mechanism for maintain-ing a first-come ih-st-serve queue of requests for a syncbit is proposed. This queueing mechanism aiiows for a very efEcient implementation of, as well as fair access to, binary semaphores. We also Propose t0 implement Fetch-and-Add with combining in software rather than hardware. This allows an architecture to scale to a huge number of processors while avoiding the cost of hardware combining. Scenarios for common synchronization events such as work queues and barriers are presented to demonstrate the generality and ease of use of the proposed primitives. The efficient implementation of the primitives is simpler if the multiprocessor has a hardware cache-consistency pro-tocol. To illustrate this point, we outline how the primitives would be implemented in the Multicube multiprocessor [GoWofB]. 1

Year: 1989
OAI identifier: oai:CiteSeerX.psu:10.1.1.135.578
Provided by: CiteSeerX
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