Abstract—In this paper, the implementation of a classical identification technique with medium computational complexity over a system with limited computing capability, is addressed. As a testbed, the Frequency-Domain Least Mean Squares (FD-LMS) algorithm  is implemented with fixed--point (finite wordlength) rather than floating--point routines. The fundamental issue of faster sampling at a reduced wordlength, compared to the case of a slower sampling rate with increased accuracy (smaller roundoff errors) is investigated in the ensuing simulation studies. This problem is typical in embedded systems (controllers) with limited number crunching capabilities, where their computational power significantly limits the maximum number of operations (multiplications and additions) that can be executed within a time interval. The results of this study point towards the need of jointly optimizing the sampling rate, the wordlength size and the complexity of the assumed filter (model) in system identification cases. Index Terms—System identification, Finite wordlength
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