The complexity of digital design and time-to-market have arose many challenges in synchronous design methodology; the need for high frequency and low skew clock distribution with its profound effect on final circuits take a lot of time and implementation cost. Asynchronous design methodology by eliminating global clock and replacing synchronization with handshaking is not yet much promising for current microelectronic industries due to the lack of expert designers and design tools. Globally Asynchronous Locally Synchronous design methodology by partitioning a full synchronous design into smaller parts which communicate trough asynchronous media can overcome lot of these problems. While partitioning as the first step in GALS design is shown to have an intense effect on final circuit quality in term of performance and power consumption, it requires itself precise abstract models for performance and power. In this work we address such a highlevel model for finding the best partitioning scheme among various options in term of performance. We modeled a Reed-Solomon Decoder with two partitioning schemes to show that our result fairly mimic the actual metrics. It is also shown that our model can also be used for power estimation in case of Reed-Solomon but we left generalized power estimation for future works
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