High-speed low-power phase-locked loops (PLLs) are an integral part of frequency synthesizers and clock recovery circuits. This paper describes the design of a 2-GHz PLL that employs a number of circuit techniques to reduce the power dissipation to 1.6 mW with a 3-V supply. Fabricated in an 18-GHz 0.6-pm BiCMOS technology, the PLL utilizes fully-differential signals to improve the rejection of common-mode disturbances. Figure 1 shows a block diagram of the PLL, a fairly standard architecture, but with the phase detector, the low-pass filter (LPF), and the voltage-controlled oscillator (VCO) merged so as to save power dissipation. The am- are driven by signals that have proper common-mode level plifier interposed between the LPF and the VCO operates and are opposite of those applied to the emitters of Q1 and at low frequencies, thus consuming negligible power. The Q2. PLL design is described in a progression starting with the The final combination of the VCOjmixer/LPF is show
To submit an update or takedown request for this paper, please submit an Update/Correction/Removal Request.